1. Technical Field
The present disclosure relates generally to information processing systems and, more specifically, to folding no-operation instruction (“NOP”) information into buffer entries for other instructions.
2. Background Art
Microprocessors often use instruction pipelining to increase instruction throughput. An instruction pipeline processes several instructions through different stages of instruction execution concurrently, using an assembly line-type approach. These instructions may be executed in a dynamically scheduled (e.g., out-of-order) processor. For instructions that are allowed to execute out of order, the instructions are retired in their original program order. Until retirement, information regarding instructions executed out of order is maintained in a structure such as, for instance, a re-order buffer (“ROB”). In-order retirement of instructions that have been executed out of order allows for precise exception handling.
Some processors, such as the Itanium® and Itanium II® microprocessors available from Intel Corporation in Santa Clara, Calif., utilize Explicitly Parallel Instruction Computing (EPIC) technology to execute multiple instructions simultaneously in order to increase instruction throughput. In such processors, several instructions (e.g., three instructions) are grouped together into aligned containers called bundles. Each bundle includes three 41-bit instructions and a format code.
If a series of instructions to be executed by the processor does not fit into one of the templates indicated by a given format code, then a no-operation instruction (referred to herein as “NOP instruction” or simply “NOP”) may be inserted into a bundle in order to execute one or two other instructions that do fit into the template. NOP instructions may also be inserted into a bundle for branch alignment reasons. If a relatively large percentage of NOP instructions appear in the code stream, computing resources may be inefficiently utilized.